Английский язык

МИНИСТЕРСТВО ОБРАЗОВАНИЯ И НАУКИ РФ 

ФЕДЕРАЛЬНОЕ ГОСУДАРСТВЕННОЕ ОБРАЗОВАТЕЛЬНОЕ УЧРЕЖДЕНИЕ  
ВЫСШЕГО ПРОФЕССИОНАЛЬНОГО ОБРАЗОВАНИЯ  
«НАЦИОНАЛЬНЫЙ ИССЛЕДОВАТЕЛЬСКИЙ ТЕХНОЛОГИЧЕСКИЙ УНИВЕРСИТЕТ «МИСиС» 

 

 
 
 

 

 

 

 
 

 

№ 2047 

Кафедра русского и иностранного языков и литературы

О.А. Кладиева 
О.Ю. Саленко 
 

Английский язык

 

Учебно-методическое пособие по научно-техническому 
переводу и реферированию 

Рекомендовано редакционно-издательским 
советом университета 

Москва 2011 

УДК 811.111 
 
К47 

Р е ц е н з е н т  
канд. филол. наук, доц. А.В. Гольдман (МПГУ) 

Кладиева, О.А. 
К47  
Английский 
язык : учеб.-метод. 
пособие 
по 
научнотехническому переводу и реферированию / О.А. Кладиева, 
О.Ю. Саленко. – М. : Изд. Дом МИСиС, 2011. – 78 с. 
ISBN 978-5-87623-464-3 

Целью учебно-методического пособия является формирование навыков 
перевода научно-технических текстов, а также говорения на заданную тему. 
Представлены материалы, направленные на формирование лингвистической 
и дискурсивной компетенций. Содержатся упражнения на овладение лексическим материалом по теме, стилистическими особенностями научной речи; 
задания на описание таблиц, графиков, рисунков и прочих типов графической информации; на обучение письменному научно-техническому переводу, 
аннотированию и реферированию научных статей, их обсуждению. 
Предназначено для студентов, обучающихся по направлению «Прикладная математика и информатика». 

УДК 811.111 

ISBN 978-5-87623-464-3 
© Кладиева О.А., 
Саленко О.Ю., 2011 

CONTENTS 

Unit 1. Mobile Supercomputers..................................................................4 
Unit 2. Chip Technologies........................................................................13 
Unit 3. Flash Memory...............................................................................24 
Unit 4. Computer Languages....................................................................34 
Unit 5. Databases......................................................................................41 
Unit 6. Search Engines .............................................................................51 
Unit 7. Web-design...................................................................................59 
Unit 8. Computer Crime ...........................................................................67 
Supplementary Materials..........................................................................75 
 

Unit 1. Mobile Supercomputers 

Warm-Up 

Before you read the text, discuss in pairs: 
Which generation of computers has already been released? Which one 
do we use? 
Will cell phones replace personal computers? 

I. Reading 

Mobile Supercomputers 

Todd Austin, David Blaauw, Scott Mahike, and Trevor Mudge, 
University of Michigan; Chaitali Chakrabarti, Arizona State University; 
Wayne Wolf, Princeton University 

Moore's law has held away over the past several decades, with the 
number of transistors per chip doubling every 18 months. As a result, a 
fairly inexpensive CPU can perform hundreds of millions of operations 
per second – performance that would have cost millions of dollars two 
decades ago. We should be proud of our achievements and rest on our laurels, right? Unfortunately, no. The human appetite for computation has 
grown even faster than the processing power that Moore's law predicted. 
We need even more powerful processors just to keep up with modem applications like interactive multimedia communications. To make matters 
more difficult, we need these powerful processors to use much less electrical energy than we have been accustomed to. 
In other words, we need mobile supercomputers that provide massive 
computational performance from the power in a battery. These supercomputers will make our personal devices much easier to use. They will perform real-time speech recognition, video transmission and analysis, and 
high-bandwidth communication. And they will do so without us having to 
worry about where the next electrical outlet will be. But to achieve this 
functionality, we must rethink the way we design computers. Rather than 
worrying solely about performance, with the occasional nod to power 
consumption and cost, we need to judge computers by their performancepower-cost product. This new way of looking at processors will lead us to 
new computer architectures and new ways of thinking about computer 
system design. 

A mobile computing world 
Untethered1 digital devices are already ubiquitous. The world has more 
than 1 billion active cell phones, each a sophisticated multiprocessor. 
With sales totaling about $400 million every year, the cell phone has arguably become the dominant computing platform, a candidate for replacing the personal computer. 
We expect to see both the types and numbers of mobile digital devices 
increase in the near future. New devices will improve on the mobile phone 
by incorporating advanced functionality, such as always-on Internet access and human-centric interfaces that integrate voice recognition and 
videoconferencing. We also anticipate the emergence of relatively simple, 
disposable devices that support the pervasive computing infrastructure – 
for example, sensor network nodes. The requirements of low-end devices 
are increasing exponentially, and computer architectures must adapt to 
keep up. 
Some elements of high-end devices are already present in 3G cell 
phones from the major manufacturers. High-end PDAs also include an 
amazing range of features, such as networking and cameras. 

Supercomputer requirements 
A mobile supercomputer will employ natural I/O interfaces to the mobile user. For example, input could come through a continuous real-time 
speech-processing component. Device output will include high-bandwidth 
graphics display, either as a semitransparent heads-up display or an ocular 
interface such as a retinal projector. An audio channel will support output 
for audio reception and sound cues. Finally, the device will include a 
high-bandwidth wireless interface for network and telecommunication 
access. 
This platform will have to execute many computationally intensive applications: soft radio, cryptography, augmented reality, speech recognition, and mobile applications such as e-mail and word processing. We expect this platform to require about 16 times as much computing horsepower as a 2-GHz Intel Pentium 4 processor, for a total performance payload of 10,000 SPECInt benchmark units (www.specbench.org). 
To remain mobile, the device must achieve this extremely high performance using only a small battery for power. Given the slow growth 
trend for batteries – 5 percent capacity increase per year – we estimate 
that a mobile supercomputer (circa 2006) will require a 1,475 mA-hr battery weighing 4 oz. With a five-day battery lifetime under a 20 percent 
_________ 
1 Unlinked, non-stationary. 

duty cycle (peak load versus standby), we estimate that the system's peak 
power requirement must not exceed 75 mW. 

Performance and power trends 
Unfortunately, mobile supercomputing's requirements are in contrast to 
the trends we see in both computer architecture and power for future devices. 
Figure 1.1 shows the trends in performance, measured in SPECInt, for 
a family of Intel x86 processors. Figure 1.2 shows the power consumption 
trends in the same processors. The graphs represent the published data for 
processors ranging from the 386 (in 1990) to the Pentium 4 (in 2002) in 
roughly two-year steps. The predicted trends through 2008 are derived 
from the 2003 edition of the International Technology Roadmap for Semiconductors (http://public.itrs.net/). 

 

Figure 1.1. Performance trends for desktop processors 

 

Figure 1.2. Power trends for desktop processors 

The star on each graph indicates our mobile supercomputer's performance and power requirements. Clearly, the trends will not meet mobile 
supercomputing demands anytime soon – and without significant innovation, perhaps they never will. 

General-purpose limits 
For more than three decades, architects have lavished attention on the 
design and optimization of general-purpose processors. As a result, current designs feature many advanced techniques such as superpipelining, 
superscalar execution, dynamic scheduling, multilevel memory caching, 
and aggressive speculation. Combined with fabrication technology improvements, these optimizations have resulted in a steady doubling of 
processor performance every 18 months. 
But a growing body of evidence suggests that general-purpose processor optimizations are diminishing in value. A study examining the scalability of future general-purpose processor designs (V. Agarwal et al., 
"Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures", Proc. 27th Ann. Int'l. Symp. Computer Architecture (ISCA 
00), IEEE CS Press, 2000, pp. 248–259) identified two kinds of generalpurpose processor optimizations: 
• increased clock speed through pipelining, and 
• higher instruction throughput via instruction-level parallelism. 
The combined strength of these optimizations has led to the industry's 
impressive performance gains. 
The study points out that clock-rate improvements from pipelining 
must soon diminish because current designs have little logic within pipe 
stages. As such, latch delay and clock skew will soon dominate the clock 
period. The pipeline curve in Figure 1.1 illustrates this leveling off. For 
example, Intel's Pentium IV microprocessor has only 12 fanout-of-four 
(FO4) gate delays per stage, leaving little logic that can be bisected to 
produce higher clocked rates. 
The negative trend of the instruction-level parallelism curve in Figure 1.1 
suggests that increased instruction throughput cannot make up for anticipated clocking limits. The Pentium IV microprocessor achieves only 
about 80 percent of its predecessor Pentium Ill's instruction throughput for 
some applications (measured in SPECInt/Mhz for the same technology). 
As architectural optimizations reach their limits, they threaten a primary source of value in the computer industry, namely ongoing performance increases. 

Nanometer impedances 
Circuit-level effects in nanometer devices are also a leading barrier to 
continued performance scaling. Short-channel effects already prevent gate 
delay from scaling with feature size as originally expected. Figure 1.1 
shows the technology curve flattening. Capacitive and inductive coupling 
and increased interconnect lengths pose a serious difficulty for fast signal 
transmission across the die. 
Furthermore, as Figure 1.2 shows, the sharp rise in static leakage current in nanometer designs is impeding continued improvements in processor power consumption. The leakage current originates in a dramatic increase in both subthreshold current and gate-oxide leakage current. In fact, 
static power consumption is now a primary issue in deep submicron design and is projected to account for as much as 50 percent of the total 
power dissipation for high-end processors in 90-nm technology. 

Revolutionary changes 
In mobile applications, a device can be in standby mode a significant 
portion of the time. In this case, leakage power dominates total power dissipation and threatens the ability to meet the power requirements for highperformance mobile processors. It is becoming clear that incremental improvements within the architecture and circuit subdomains are not going 
to deliver the extra performance and power efficiency that high-end mobile applications will demand. 
Furthermore, future generations of VLSI technology will not provide 
the reliable operation that we have so long assumed. The small size of future devices will make them vulnerable to radiation-induced upsets, circuit 
noise, and other factors that produce enough operational, transient failures 
to require architectural designs that can compensate for them. This means 
diverting a significant amount of the processor's computational effort to 
check the results. Thus, we must be even more clever about how we 
squeeze performance out of our machines, particularly since all that 
checking logic consumes energy that we can ill afford to lose. 

Joint optimizations 
To build practical mobile supercomputers, system architects need to 
jointly optimize across algorithms, architectures, and circuits. We don't 
have all the answers today about how to solve all the problems inherent in 
mobile supercomputing, but we believe that we have identified some useful approaches. 
We can control tradeoffs in a vertically integrated manner: 
• microarchitectures that can take advantage of advanced circuit features,